/* SPDX-License-Identifier: GPL-2.0 */
#include <linux/types.h>

#if defined(CONFIG_ARCH_LOMBO_N7V3)
#define LOMBO_UART_NUM  (5)
#elif defined(CONFIG_ARCH_LOMBO_N7V5)
#define LOMBO_UART_NUM  (6)
#elif defined(CONFIG_ARCH_LOMBO_N9V1)
#define LOMBO_UART_NUM  (9)
#elif defined(CONFIG_ARCH_LOMBO_N9V3)
#define LOMBO_UART_NUM  (6)
#elif defined(CONFIG_ARCH_LOMBO_N5V0)
#define LOMBO_UART_NUM  (2)
#elif defined(CONFIG_ARCH_LOMBO_N5V1)
#define LOMBO_UART_NUM  (6)
#elif defined(CONFIG_ARCH_LOMBO_N9V2)
#define LOMBO_UART_NUM  (2)
#endif

#define RTS_DE_A_THR_VALUE         (0x30)
#define RTS_A_THR__VALUE           (0x10)

#define UART0_RTS_DE_A_THR_VALUE   (0xC0)
#define UART0_RTS_A_THR__VALUE     (0x40)

/* register offset define */
#define LOMBO_UART_BD              (0x10)
#define LOMBO_UART_CTL             (0x14)
#define LOMBO_UART_FIFO_CTL        (0x18)
#define LOMBO_UART_DMA_CTL         (0x1C)
#define LOMBO_UART_RAR             (0x20)
#define LOMBO_UART_TAR             (0x24)
#define LOMBO_UART_RS485DET        (0x30)
#define LOMBO_UART_RS485TAT        (0x34)
#define LOMBO_UART_RTS_TH_CFG      (0x38)
#define LOMBO_UART_STATUS          (0x40)
#define LOMBO_UART_FIFO_STATUS     (0x44)
#define LOMBO_UART_INT_EN          (0x50)
#define LOMBO_UART_INT_PD          (0x54)
#define LOMBO_UART_INT_CLR         (0x58)
#define LOMBO_UART_RXD             (0x80)
#define LOMBO_UART_TXD             (0x84)

/* Interrupt Enable Register */
#define LOMBO_UART_RX_BI_E         (BIT(18))
#define LOMBO_UART_RX_FE_E         (BIT(17))
#define LOMBO_UART_RX_PE_E         (BIT(16))
#define LOMBO_UART_RTX_A_E         (BIT(15))
#define LOMBO_UART_RTX_DE_A_E      (BIT(14))
#define LOMBO_UART_RX_UN_E         (BIT(11))
#define LOMBO_UART_RX_OV_E         (BIT(10))
#define LOMBO_UART_TX_DONE_E       (BIT(4))
#define LOMBO_UART_CTS_E           (BIT(2))
#define LOMBO_UART_RX_FULL_E       (BIT(1))
#define LOMBO_UART_TX_EMPTY_E      (BIT(0))

/* Interrupt Pending Register */
#define LOMBO_UART_RX_BI           (BIT(18))
#define LOMBO_UART_RX_FE           (BIT(17))
#define LOMBO_UART_RX_PE           (BIT(16))
#define LOMBO_UART_RTX_A           (BIT(15))
#define LOMBO_UART_RTX_DE_A        (BIT(14))
#define LOMBO_UART_RX_UN           (BIT(11))
#define LOMBO_UART_RX_OV           (BIT(10))
#define LOMBO_UART_TX_DONE         (BIT(4))
#define LOMBO_UART_CTS             (BIT(2))
#define LOMBO_UART_RX_FULL         (BIT(1))
#define LOMBO_UART_TX_EMPTY        (BIT(0))

/* Interrupt Clear Register */
#define LOMBO_UART_RX_BI_CLR      (BIT(18))
#define LOMBO_UART_RX_FE_CLR      (BIT(17))
#define LOMBO_UART_RX_PE_CLR      (BIT(16))
#define LOMBO_UART_RX_UN_CLR      (BIT(11))
#define LOMBO_UART_RX_OV_CLR      (BIT(10))
#define LOMBO_UART_RX_FULL_CLR    (BIT(1))

/* Line Status Rigster */
#define LOMBO_UART_SR_PE          (BIT(12))
#define LOMBO_UART_SR_OE          (BIT(13))
#define LOMBO_UART_SR_BI          (BIT(14))
#define LOMBO_UART_SR_BRK_ERROR_BITS (0x5000) /* BI, PE bits */

enum uart_rx_trg {
	RX_TRG_1CH,  /* 1 character in the FIFO */
	RX_TRG_4CH,  /* 4 character in the FIFO */
	RX_TRG_8CH,  /* 8 character in the FIFO */
	RX_TRG_1_4,  /* FIFO 1/4 full */
	RX_TRG_1_2,  /* FIFO 1/2 full */
	RX_TRG_FULL  /* FIFO 2 less than full */
};

enum uart_tx_trg {
	TX_TRG_EMP,  /* FIFO empty */
	TX_TRG_2CH,  /* 2 character in the FIFO */
	TX_TRG_1_4,  /* FIFO 1/4 full */
	TX_TRG_1_2   /* FIFO 1/2 full */
};

enum uart_rs485_mode {
	FULL_DP_MODE, /* Full Duplex Mode */
	SW_HALF_DP_MODE, /* Software-Controlled Half Duplex */
	HW_HALF_DP_MODE, /* Hardware-Controlled Harf Duple */
};

extern void csp_uart_baud_rate_config(void *base, int clk_in, int baud);
extern void csp_uart_putchar(void *base, int c);
extern u32  csp_uart_getchar(void *base);
extern void csp_uart_dls_config(void *base, int bits);
extern void csp_uart_stop_config(void *base, int stop);
extern void csp_uart_parity_enable(void *base, int parity);
extern void csp_uart_set_parity_odd(void *base, int odd);
extern void csp_uart_reset(void *base);
extern void csp_uart_set_break_ctrl(void *base, u32 bc);
void csp_uart_rts_de_assert_threshold_cfg(void *base, u32 rts_de_val);
void csp_uart_rts_assert_threshold_cfg(void *base, u32 rts_a_val);
extern u32  csp_uart_is_auto_flow(void *base);
extern void csp_uart_set_auto_flow(void *base, int afce);
extern void csp_uart_set_rts(void *base);
extern void csp_uart_tx_fifo_trg_config(void *base, int fill_level);
extern void csp_uart_rx_fifo_trg_config(void *base, int fill_level);
extern void csp_uart_tx_fifo_reset(void *base);
extern void csp_uart_rx_fifo_reset(void *base);
extern u32  csp_uart_get_sr(void *base);
extern u32  csp_uart_tx_empty(void *base);
extern u32  csp_uart_rx_empty(void *base);
extern u32  csp_uart_is_cts(void *base);
extern u32  csp_uart_tx_fifo_not_full(void *base);
extern u32  csp_uart_irq_save(void *base);
extern void csp_uart_irq_restore(void *base, u32 irq);
extern void csp_uart_irq_disable(void *base);
extern void csp_uart_tx_irq_config(void *base, u32 enable);
extern void csp_uart_rx_irq_disable(void *base);
extern void csp_uart_irq_enable(void *base);
extern u32  csp_uart_is_tx_empty_trg(void *base);
extern u32  csp_uart_is_rx_or_data_avl(void *base);
extern u32  csp_uart_is_cts_pend(void *base);
extern u32  csp_uart_is_tx_done_pend(void *base);
extern void csp_uart_clear_tx_empty_trg(void *base);
extern void csp_uart_clear_rx_or_data_avl(void *base);
extern void csp_uart_clear_cts(void *base);
extern void csp_uart_clear_tx_done_pend(void *base);
extern u32 csp_uart_get_tx_fill_level(void *base);
extern u32 csp_uart_get_rx_fill_level(void *base);
extern void csp_uart_tx_en(void *base, int enable);
extern void csp_uart_rx_en(void *base, int enable);
extern void csp_uart_rs485_enable(void *base, u32 enable);
extern u32  csp_uart_rs485_mode_config(void *base, enum uart_rs485_mode mode);
extern u32  csp_uart_rs485_de_enable(void *base, u32 enable);
extern u32  csp_uart_rs485_re_enable(void *base, u32 enable);
extern void csp_uart_rs485_de_pol_enable(void *base, u32 enable);
extern void csp_uart_rs485_re_pol_enable(void *base, u32 enable);
extern void csp_uart_tx_dma_threshold_cfg(void *base, u32 val);
u32 csp_uart_tx_dma_enable(void *base, u32 enable);
